You Will Need

• Macintosh SE (any revision) with original 68000 CPU
• PDS Accelerator Card kit (PCB + all components)
• JTAG programmer (any FTDI-based, or Lattice HW-USBN-2B)
• System 7.1 or 7.5.x boot floppy or hard drive
• MODE32 or 32-Bit System Enabler (for 32-bit addressing)

Tools

• Soldering iron with fine tip (0805 SMD + through-hole)
• Solder (0.5–0.8 mm for SMD, 0.8–1.0 mm for THT)
• Flux pen or paste
• Tweezers (fine-tip for 0805 passives)
• Multimeter
• Long-shaft Phillips screwdriver + Torx T-15
• Anti-static wrist strap
• CRT discharge tool
• Magnifying glass or loupe (for TQFP-144 inspection)

Recommended Experience

This is an intermediate-to-advanced build. You should be comfortable with:

• SMD soldering (0805 passives, TSSOP-20, SOT-223)
• Fine-pitch soldering (TQFP-144 at 0.5 mm pitch — the CPLD)
• PGA socket insertion (CPU and FPU)
• Using a JTAG programmer

See the Pi HAT guide CRT safety section for full discharge instructions. The same procedure applies here. Always discharge before working inside the case.

Solder all SMD parts before through-hole components. Work from smallest to largest.

Passives (0805)

1. C1–C4 (100nF) — CPU decoupling, near U1
2. C5–C8 (100nF) — CPLD decoupling, near U3
3. C9–C12 (100nF) — SDRAM decoupling, near U4/U5
4. C13–C18 (100nF) — level shifter decoupling, near U6–U12
5. C19–C20 (100nF) — FPU decoupling, near U2
6. C23–C24 (22pF) — crystal load caps, near Y1
7. R1–R4 (10K) — pull-up resistors
8. R5 (3.3K) + R6 (6.8K) — clock voltage divider

ICs (SMD)

1. U10 (AMS1117-3.3, SOT-223) — LDO voltage regulator. Tab/heatsink pad faces the board edge.
2. U6–U9, U11–U12 (SN74LVC8T245, TSSOP-20) — level shifters. Pin 1 dot on IC matches silkscreen.
3. U4, U5 (IS42S16320F, TSOP-II-54) — SDRAM. Pin 1 notch matches silkscreen. Use plenty of flux.
4. U3 (MachXO2-2000HC, TQFP-144) — CPLD. This is the hardest part. Align carefully, tack one corner, verify alignment under magnification, then drag-solder each side. Check for bridges.
5. Y1 (50 MHz, HC49-SD) — crystal oscillator.

Bulk Capacitors

1. C21–C22 (100µF electrolytic, radial 6.3 mm) — bulk decoupling near LDO. Polarized! Match “+” to silkscreen.

1. J2 — JTAG header (2×5 pin header, 2.54 mm)
   Solder the 10-pin header. Pin 1 marked on silkscreen.
2. U1 — MC68030RC50 (PGA-128)
   The PCB has 1.0 mm drill holes on a 2.54 mm grid — compatible with both direct soldering and machined-pin PGA sockets.
   
   With socket (recommended): Solder the PGA-128 socket first (e.g., Preci-Dip 510-87-128-13-041101 or Mill-Max 510-43-128-13-041001). Align pin A1 to silkscreen. Solder all pins from the back. Then insert the CPU into the socket — align the notched corner with pin A1.
   
   Direct solder: Align pin A1 (marked with dot on IC and silkscreen). The CPU has a notched corner for orientation. Press firmly into holes and solder from the back.
   Double-check orientation before soldering — direct-soldered PGA parts are not easily reworkable.
3. U2 — MC68882RC50 (PGA-68)
   Same as U1. Socket option: Mill-Max 510-93-068-10-041001 or Phoenix Enterprises HWS3728.
   Align pin A1 to silkscreen. Notched corner = pin 1 area.
4. J1 — DIN41612 C 3×32 Female (96-pin connector)
   This is the PDS edge connector. It mounts vertically along the left edge of the board.
   The connector has alignment pins/pegs — make sure they seat into the board holes before soldering.
   Solder a few pins first to tack it straight, then solder all 96 pins. Use generous heat — these are large thermal-mass pins.

Before applying power, check:

• No shorts between +3.3V and GND (check at U10 output vs GND)
• No shorts between +5V and GND (check at J1 power pins)
• U3 (CPLD) — no solder bridges between adjacent pins (inspect all 4 sides)
• U4/U5 (SDRAM) — no bridges on fine-pitch TSOP pins
• U1 pin A1 and U2 pin A1 correctly oriented
• C21/C22 polarity correct
• J1 connector straight and fully seated
• All level shifters (U6–U9, U11–U12) oriented correctly (pin 1 dot matches silkscreen)

Power Test (Without CPU/FPU)

Before inserting U1 and U2 (if socketed), apply +5V to the PDS connector power pins and verify:

• +3.3V present at U10 output (should be 3.30V ± 0.05V)
• No excessive current draw (< 50 mA with no CPU inserted)
• 50 MHz oscillation present at Y1 (check with scope if available)

The MachXO2 CPLD must be programmed with the bus arbitration firmware before the card will function.

Connect JTAG

Connect your JTAG programmer to J2:

J2 Pin	Signal	JTAG Function
1	TCK	Test Clock
2	GND	Ground
3	TDO	Test Data Out
4	GND	Ground
5	TDI	Test Data In
6	GND	Ground
7	TMS	Test Mode Select
8	GND	Ground
9	VCC	Target power sense (3.3V)
10	GND	Ground

Programming

Use Lattice Diamond Programmer or openFPGALoader:

The CPLD stores its configuration in on-chip flash — it retains programming without external power. Program once, done forever (unless you want to update firmware).

Verify Programming

After programming, the CPLD DONE pin should go high (visible as LED on some programmers). You can also read back the JEDEC file to verify.

1. Remove the Mac SE rear case (4 Torx T-15 screws).
2. Discharge the CRT.
3. Locate the PDS slot on the logic board — it's the 96-pin DIN41612 connector near the top-right of the board (when viewed from the back).
4. Align the accelerator card's J1 connector with the PDS slot. Pin 1 (row A, position 1) is marked on both the card and the logic board.
5. Press the card firmly and evenly into the slot until fully seated. The card should be perpendicular to the logic board.
6. The card may need a support bracket or standoff to prevent flexing. Use a nylon standoff if the card droops.
7. Verify the card is not touching the CRT neck board or analog board components.

Clearance Check

The Mac SE case interior has limited space. Verify:

• Card does not contact the CRT yoke or neck board
• Card does not contact the floppy drive cage
• No components on the card are touching the case shell
• The DIN connector is fully seated (no exposed pin metal visible)

32-Bit Addressing

The 68030's 32-bit address bus requires 32-bit clean ROMs or a software enabler:

• System 7.1: Install MODE32 (free from Connectix, now abandonware)
• System 7.5+: 32-bit addressing is built in. Enable it in the Memory control panel.

Memory Control Panel

1. Open Apple Menu → Control Panels → Memory
2. Set “32-Bit Addressing” to On
3. Set “Virtual Memory” to On if desired (the 64 MB RAM usually makes this unnecessary)
4. Restart

FPU Support

The MC68882 FPU is automatically detected by System 7. Applications that use floating-point math (Photoshop, Excel, Mathematica) will automatically use the hardware FPU. No driver installation needed.

Accelerator INIT (Optional)

An optional System Extension will be provided that adds a control panel for:

• Enabling/disabling the cache
• Switching between 25 MHz and 50 MHz operation
• Viewing memory test results
• CPLD firmware version display

Place the INIT file in the System Folder → Extensions folder and restart.

1. With the card installed and CPLD programmed, close the Mac SE case.
2. Power on. You should see the normal Mac startup chime and happy Mac icon.
3. The startup sequence will be noticeably faster than stock — the 50 MHz CPU accelerates even the ROM boot routines.
4. Once booted, open “About This Macintosh” from the Apple menu. You should see:
   • Total Memory: 64 MB (or 68 MB with built-in RAM included)
   • The system should report a 68030 processor

Benchmarking

Run Speedometer 3.x or Norton System Info to verify performance. Expected results:

Test	Stock SE (8 MHz 68000)	With Accelerator (50 MHz 68030)
CPU	1.0x	~15–20x
FPU	N/A	Present (68882)
Disk	Unchanged	Unchanged (disk is on PDS bus)
Memory	~2 MB/s	~50–100 MB/s (SDRAM burst)

Symptom	Check
No startup chime, no video	Card may not be fully seated in PDS slot — remove and reseat. Check for shorts on the card (especially U3 TQFP pins). Try booting without the card to confirm Mac SE still works.
Sad Mac icon (error code)	Memory test failure. Note the error code — upper word is the test, lower is the failing address. Could indicate bad SDRAM solder joint or incorrect CPLD firmware. Reseat CPU/FPU if socketed.
Boots but only shows 4 MB RAM	32-bit addressing not enabled. Install MODE32 or enable in Memory control panel. Verify CPLD firmware includes memory controller.
Crashes or freezes during use	Check decoupling capacitors — missing or cold-jointed caps cause instability at 50 MHz. Check clock signal integrity (50 MHz crystal — poor solder joints cause jitter). Try running at 25 MHz (if firmware supports speed switching).
CPLD won't program	Verify JTAG connections (TCK, TDI, TDO, TMS). Check that 3.3V power is present on the card. Try lower JTAG clock speed. Verify no shorts on CPLD pins.
FPU not detected	Verify MC68882 is oriented correctly (pin A1). Check solder joints on PGA pins. Run an FPU test utility (e.g., FPU Checker).
System runs but no speed improvement	The accelerator may not have taken over the bus. Check CPLD firmware. Verify bus arbitration signals (/BR, /BG, /BGACK) with a logic analyzer. Check that the 68030 is actually clocked (50 MHz on CLK pin).